--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   20:47:16 10/09/2013
-- Design Name:   
-- Module Name:   C:/Users/Ling Chun Kai/Documents/NUS modules/CG3207/Lab/CG3207/new_divider_test.vhd
-- Project Name:  LAB2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: divider_signed
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY new_divider_test IS
END new_divider_test;
 
ARCHITECTURE behavior OF new_divider_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT divider_signed
    PORT(
         clk : IN  std_logic;
         start_division : IN  std_logic;
         numerator : IN  std_logic_vector(31 downto 0);
         denominator : IN  std_logic_vector(31 downto 0);
         is_signed : IN  std_logic;
         quotient : OUT  std_logic_vector(31 downto 0);
         remainder : OUT  std_logic_vector(31 downto 0);
			
			div_0_flag : out STD_LOGIC;
			overflow_flag : out STD_LOGIC
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal start_division : std_logic := '0';
   signal numerator : std_logic_vector(31 downto 0) := (others => '0');
   signal denominator : std_logic_vector(31 downto 0) := (others => '0');
   signal is_signed : std_logic := '0';

 	--Outputs
   signal quotient : std_logic_vector(31 downto 0);
   signal remainder : std_logic_vector(31 downto 0);
	signal div_0_flag : STD_LOGIC;
	signal overflow_flag : STD_LOGIC;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: divider_signed PORT MAP (
          clk => clk,
          start_division => start_division,
          numerator => numerator,
          denominator => denominator,
          is_signed => is_signed,
          quotient => quotient,
          remainder => remainder,
			 
			 div_0_flag => div_0_flag,
			 overflow_flag => overflow_flag
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;

      -- insert stimulus here 
		is_signed <= '0';

		-- TEST 1a: 12345678h / 3h = 6117228h
		numerator <= x"12345678";
		denominator <= x"00000003";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1b : 12345679h / 3h = 6117228h + 1h
		numerator <= x"12345679";
		denominator <= x"00000003";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1c : 1234567Ah / 3h = 6117228h + 2h
		numerator <= x"1234567A";
		denominator <= x"00000003";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1d : F000BEAFh / F000BEAFh = 1h + R 0h
		--- Divide by itself
		numerator <= x"F000BEAF";
		denominator <= x"F000BEAF";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1e : 0A0B0D19h / 0A0B0D1Ah = 0h + 0A0B0D19h
		--- Divide by itself
		numerator <= x"0A0B0D19";
		denominator <= x"0A0B0D1A";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1f : 01010102h / 00000000h = DIVIDE BY ZERO - need to handle.
		numerator <= x"43741FEA";
		denominator <= x"00000000";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1e : AAAABBBBh / 11119876h = 9h + R 110c5f95
		numerator <= x"AAAABBBB";
		denominator <= x"11119876";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		------------------
		-- signed cases
		------------------
		is_signed <= '1';
		
		-- Test 2ai
		--- Negative / positive
		--- Gives Q = FFFFFFFc (-4) and R = 	EEF11d93 (some negative number)
		numerator <= x"AAAABBBB";
		denominator <= x"11119876";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- Test 2aii
		-- Negative/positive extreme case
		-- gives Q = 80000000, R = 0
		numerator <= x"80000000";
		denominator <= x"00000001";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- Test 2aiii
		-- Negative/positive extreme case
		-- gives Q = C0000000 R = 0
		numerator <= x"80000000";
		denominator <= x"00000002";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- Test 2aiv
		-- Negative/positive extreme case
		-- gives Q = ....
		-- OVERFLOW - KABOOOOOOOOOOOOOOOOOOOOOOOOOOOOM!!!!!!
		numerator <= x"80000000";
		denominator <= x"FFFFFFFF";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
				
		-- Test 2av
		-- Negative/positive random case
		-- gives Q = FFFFFFE9 (-23d) and R = fdf5675c (-34248868)
		-- SHOULD GIVE OVERFLOW
		numerator <= x"82309A13"; -- -2110744045 d
		denominator <= x"0561999F"; -- 90282399 d
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
	
		-- Test 2bai
		-- Positive/Negative , random
		-- gives Q = FFFFFFE6 (-26) and R = 0122162C
		numerator <= x"2345789A"; -- 591755418 d
		denominator <= x"FEAFDEAD"; -- -22028627 d
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- Test2baii
		-- Positive/Negative, extreme case
		-- should give Q = 0, R = 0
		numerator <= x"00000000"; -- 0d
		denominator <= x"DDDDAAAA"; -- -whatever...
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- Test2baiii
		-- Positive/Negative, extreme case
		-- should give Q = 89ABCDF0, R = 0
		numerator <= x"76543210"; -- 1985229328 d
		denominator <= x"FFFFFFFF"; -- -1
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
	
		-- Test2baiv
		-- Positive/Negative, extreme case
		-- should give Q = 0, R = 00101234h
		numerator <= x"00101234"; -- small positive number
		denominator <= x"88888888"; -- big negative number
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- Test2ci
		-- Negative/Negative, random case
		-- Q = 1, R = ddba9900h
		numerator <= x"89888889"; -- -1987540855
		denominator <= x"ABCDEF89"; -- -1412567159
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- Test2cii
		-- Negative/Negative, extereme case
		-- SHOULD GIVE OVERFLOW!!!!
		numerator <= x"80000000"; -- MINIMUM NUMBER
		denominator <= x"FFFFFFFF"; -- -1
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- Test2ciii
		-- Negative/Negative, extereme case
		-- Q = 7FFFFFFFh = 2147483647d , R = 0
		numerator <= x"80000001"; -- MINIMUM NUMBER + 1
		denominator <= x"FFFFFFFF"; -- -1
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- Test2civ
		-- Negative/Negative, random case
		-- Q = 5A44F8h = 5915896d, R = FFFFFF3C
		numerator <= x"AAAACCCC"; -- -1431647028
		denominator <= x"FFFFFF0E"; -- -242
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- Test2cv
		-- Negative/Negative, extereme case
		-- ALMOST OVERFLOW. but no banana... Q = 40000000
		numerator <= x"80000000"; -- MINIMUM NUMBER
		denominator <= x"FFFFFFFE"; -- -2
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		--- TODO: Test positive/positive case, ie. Test2d
		
      wait;
   end process;

END;
